A Delay Locked Loop (DLL) is a digital circuit designed to support high-bandwidth data rates between devices. It provides zero propagation delay, low-clock skew between output clock signals throughout a device, and advanced clock domain control. The DLL is similar to a phase locked loop with the main difference being the absence of the voltage controlled oscillator. The DLL can be used to change the phase of a clock signal and can be viewed as a negative-delay gate in the path of the clock signal.
The typical DLL includes a delay chain composed of plural delay gates connected in series. The input of the chain is coupled to the clock that is to be delayed. A multiplexer is connected to each stage of the delay chain, and the selector of the multiplexer is automatically updated by a control circuit to produce the negative delay effect. The output of the DLL circuit is the negatively delayed clock signal. The DLL operates by comparing the phase of one of its outputs to the input clock to generate an error signal, which it then integrates and feeds back as the control signal to the delay elements within the DLL. The integration allows the error to go to zero while keeping the control signal where it needs to be for phase lock.
Conventional methods of testing the phase a DLL output vis a vis the source clock use a digital scope. A chip under test having a DLL is mounted on a PCB, and connected to a digital scope via cabling. Mismatches within the clock paths degrade the measurement accuracy when the operating frequency is in the gigahertz level and beyond. For this reason, some chips with DLL circuits are provided with on-chip measurements circuits. These on-chip measurements circuits convert a detected phase difference to a DC voltage value. This voltage value can then be read with a voltmeter. This approach addresses the above-described clock path matching problem of the PCB but suffers from its own problems. The conventional on-chip phase difference measurement circuit uses a XNOR gate, period-to-current converter and then current-to-voltage converter. The XNOR gate transforms the phase difference into a timing width using NMOS and PMOS transistors. One problem with this approach is that the duty cycle of the output period can be shifted due to process, voltage and temperature (PVT) corners. A second problem with this approach is that the synthesized frequency of the XNOR is not twice that of the input frequency due to limitations on the device speed. This makes the XNOR appropriate only for low frequency operation less than 100 MHz.
Improved DLL measurements techniques for high speed applications and devices are desired.